TMS320C28x 32-bit DSP core at 100 MHz

• IEEE 754 Floating-Point Unit (FPU)

  • Support for Fast Integer Division (FINTDIV)

• Trigonometric Math Unit (TMU)

  • Support for Nonlinear Proportional Integral Derivative (NLPID) control

• CRC Engine and Instructions (VCRC)

• Ten hardware breakpoints (with ERAD)

On-chip memory

• 128KB (64KW) of flash (ECC-protected)

• 24KB (12KW) of RAM (ECC or parity-protected)

• Dual-zone security

Clock and system control

• Two internal zero-pin 10-MHz oscillators

• On-chip crystal oscillator or external clock input

• Windowed watchdog timer module

• Missing clock detection circuitry

• Dual-clock Comparator (DCC)

Single 3.3-V supply

• Internal VREG generation

• Brownout reset (BOR) circuit

System peripherals

• 6-channel Direct Memory Access (DMA) controller

• 39 individually programmable multiplexed General-Purpose Input/Output (GPIO) pins

• 16 digital inputs on analog pins

• Enhanced Peripheral Interrupt Expansion (ePIE)

• Multiple low-power mode (LPM) support

• Embedded Real-time Analysis and Diagnostic (ERAD)

• Unique Identification (UID) number

Communications peripherals

• One Power-Management Bus (PMBus) interface

• Two Inter-integrated Circuit (I2C) interfaces

• One Controller Area Network (CAN) bus port

• Two Serial Peripheral Interface (SPI) ports

• One UART-compatible Serial Communication Interface (SCI)

• Two UART-compatible Local Interconnect Network (LIN) interfaces

• Fast Serial Interface (FSI) with one transmitter and one receiver (up to 200Mbps)

Analog system

• Two 3.45-MSPS, 12-bit Analog-to-Digital Converters (ADCs)

  • Up to 16 external channels

  • Four integrated Post-Processing Blocks (PPB) per ADC

• Four windowed comparators (CMPSS) with 12-bit reference Digital-to-Analog Converters (DACs)

  • Digital glitch filters

Enhanced control peripherals

• 14 ePWM channels with eight channels that have high-resolution capability (150-ps resolution)

  • Integrated dead-band support

  • Integrated hardware trip zones (TZs)

• Three Enhanced Capture (eCAP) modules

  • High-resolution Capture (HRCAP) available on one of the three eCAP modules

• Two Enhanced Quadrature Encoder Pulse (eQEP) modules with support for CW/CCW operation modes

Configurable Logic Block (CLB)

• Augments existing peripheral capability

• Supports position manager solutions

Host Interface Controller (HIC)

• Access to internal memory from an external host

Background CRC (BGCRC)

• One cycle CRC computation on 32 bits of data

晶片方塊圖:

• 連接晶片方塊圖