TMS320C28x 32-bit CPU

• 120 MHz

• IEEE 754 single-precision Floating-Point Unit (FPU)

• Trigonometric Math Unit (TMU)

Programmable Control Law Accelerator (CLA)

• 120 MHz

• IEEE 754 single-precision floating-point instructions

• Executes code independently of main CPU

On-chip memory

• 512KB (256KW) of flash (ECC-protected)

• 100KB (50KW) of RAM (ECC-protected or parity-protected)

• Dual-zone security supporting third-party development

• Unique identification number

Clock and system control

• Two internal zero-pin 10-MHz oscillators

• On-chip crystal oscillator

• Windowed watchdog timer module

• Missing clock detection circuitry

3.3-V I/O with available internal voltage regulator for 1.2-V core supply

System peripherals

• External Memory Interface (EMIF) with ASRAM and SDRAM support

• 6-channel Direct Memory Access (DMA) controller

• Up to 97 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins with input filtering

• Expanded Peripheral Interrupt controller (ePIE)

• Multiple Low-Power Mode (LPM) support with external wakeup

Communications peripherals

• USB 2.0 (MAC + PHY)

• Two Controller Area Network (CAN) modules (pin-bootable)

• Three high-speed (up to 30-MHz) SPI ports (pin-bootable)

• Two Multichannel Buffered Serial Ports (McBSPs)

• Four Serial Communications Interfaces (SCI/UART) (pin-bootable)

• Two I2C interfaces (pin-bootable)

Analog subsystem

• Up to three Analog-to-Digital Converters (ADCs)

  • 12-bit mode

    • 3.1 MSPS each (up to 9.3-MSPS system throughput)

    • Single-ended inputs

    • Up to 17 external channels

  • Single Sample-and-Hold (S/H) on each ADC

  • Hardware-integrated post-processing of ADC conversions

    • Saturating offset calibration

    • Error from setpoint calculation

    • High, low, and zero-crossing compare, with interrupt capability

    • Trigger-to-sample delay capture

• Eight windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references

• Three 12-bit buffered DAC outputs

Enhanced control peripherals

• 24 PWM channels with enhanced features

• 16 High-Resolution Pulse Width Modulator (HRPWM) channels

  • High resolution on both A and B channels of 8 PWM modules

  • Dead-band support (on both standard and high resolution)

• Six Enhanced Capture (eCAP) modules

• Three Enhanced Quadrature Encoder Pulse (eQEP) modules

• Up to eight Sigma-Delta Filter Module (SDFM) input channels, 2 parallel filters per channel

  • Standard SDFM data filtering

  • Comparator filter for fast action for out of range

Configurable Logic Block (CLB)

• Augments existing peripheral capability

• Supports position manager solution