Dual Core Architecture

• Two TMS320C28x 32-Bit CPUs

• 200 MHz (5-ns Cycle Time)

• IEEE 754 Single-Precision Floating-Point Unit (FPU)

• Trigonometric Math Unit (TMU)

• Viterbi/Complex Math Unit (VCU-II)

• 16 x 16 and 32 x 32 MAC Operations

• 16 x 16 Dual MAC

• Three 32-Bit CPU Timers per Core

• Harvard Bus Architecture

• Fast Interrupt Response and Processing

• Unified Memory Programming Model

Two Programmable Control Law Accelerators

• 200 MHz (5-ns Cycle Time)

• 32-Bit Floating-Point Math Accelerator
  (IEEE 754 Single Precision)

• Executes Code Independently of Main CPU

On-Chip Memory

• Up to 1MB Flash, Up to 204KB RAM

• Boot ROM (64KB)

  • SPI, I2C, CAN, and Parallel I/O Software Boot Modes

  • Standard Math Tables

System Peripherals

• Dual 32- and 16-Bit EMIF With ASRAM and SDRAM Support

• Dual 6-Channel DMA Controller

• Up to 169 Individually Programmable, Multiplexed GPIO Pins With Input Filtering

Communications Peripherals

• USB 2.0 + PHY Port

• Support for 12-Pin 3.3 V-Compatible Universal Parallel Port (uPP) Interface

• Two CAN-Bus Ports (32 Mailboxes Each)

• Three High-Speed (40-MHz) SPI Ports With 16-Level FIFO, DMA Support, and
  CLA-Accessible

• Two Multichannel Buffered Serial Ports

• Four Serial Communications Interfaces

• Two Inter-Integrated Circuit (I2C) Interfaces

Analog Subsystem

• Four Dual-Mode Analog-to-Digital Converters

• 16-Bit Mode

  • 1.1 MSPS Each (Up to 4.4-MSPS System)

  • Differential

  • External Reference

  • Up to 9 External Channels

• 12-Bit Mode

  • 3.5 MSPS Each (Up to 14-MSPS System)

  • Single-Ended or Differential

  • External Reference

  • Up to 20 External Channels

• Single Sample-and-Hold (S/H)
  (Four-Simultaneous-S/H System)

• Integrated Post-Processing of ADC Conversions

  • Saturating Offset Calibration

  • Error From Setpoint Calculation

  • High, Low, and Zero-Crossing Compare, With Interrupt Capability

  • Trigger-to-Sample Delay Capture

• Analog Comparator/Digital-to-Analog Converter (DAC) Subsystem With Glitch Filter, for Windowed Trip Monitor and PCMC Interfaces

  • Eight Windowed Comparators With 12-Bit DAC References

• Two/Three 12-Bit Buffered DAC Outputs

Enhanced Control Peripherals

• 24 PWM Channels With Enhanced Features

• 16 High-Resolution PWM Channels

  • High-Resolution on Both A and B Channels of 8 PWM Modules

  • Dead-Band Support (on Both Standard and High-Resolution)

• Six Capture Modules

• Three Quadrature Encoder Pulse (QEP) Modules

• Two Sigma-Delta Filter Modules (SDFMs) With up to 8 Input Channels, Plus PWM Synchronization

Configurable Logic Block (CLB)

• Augments existing peripheral capability

• Supports position manager solutions